Helic to Present and Exhibit at the 1st TSMC Open Innovation Platform(R) Ecosystem Forum

SAN FRANCISCO, October 1, 2011 -

Helic Inc., the technology leader in EDA solutions for high-speed IC design has been selected by TSMC, the founder and leader of the Dedicated IC Foundry segment, to present its latest technology at the TSMC 2011 Open Innovation Platform Ecosystem Forum® on October 18^th, 2011 in San Jose Convention Centre, CA, USA, at 13.30-14.00 hrs.

Dr. Sotiris Bantas, Vice President of Technology, will present a paper with the title “A Substrate Noise Analysis and RLCK Extraction Flow for RF & High-Speed Design”. Helic, a certified EDA member of the TSMC ecosystem, is honoured to contribute to TSMC’s innovation model that combines the strengths of customers and partners under the common goal of shortening design time, minimizing time-to-volume and accelerating time-to-market. Helic is committed to support TSMC’s initiatives to promote innovation amongst all stakeholders of the semiconductor value chain. Such initiatives are well in concert with Helic’s values to strengthen partnerships with dynamic foundries and IDMs, to stimulate innovation, to constantly optimize quality and to develop the most reliable tooling backed by highest quality support in the whole EDA industry.

Dr. Sotiris Bantas commented: “Substrate coupling is one of the hot issues in nanoscale System-on-Chip (SoC) design. Building on our highly successful VeloceRaptor/X™ toolset, we have developed technology for analyzing the effects of unwanted substrate noise coupling, as part of a complete verification methodology addressing substrate as well as interconnect parasitics. At the 1^st TSMC OIP™ Ecosystem Forum, we will be presenting this methodology along with examples from the analysis of TSMC silicon, including our own testchips.”

Helic will also exhibit at the 2011 TSMC OIP Ecosystem Forum Partner Pavilion where IC designers will have the opportunity to see the latest releases of Helic’s tools adapted to address 28nm litho/CMP and variability effects. The spiral synthesis capabilities of VeloceRF™ have been implemented in TSMC’s 28nm PDKs and are already being used in production by Helic’s customers for DRC-clean, DFM-correct inductor and transformer design, for RF and high-speed SoCs at the 28nm process node.

About Helic

Helic, Inc. develops disruptive EDA technologies for RFIC and high-speed SoC design. We provide our customers with a comprehensive offering combining design tools, silicon IP and applications support, greatly reducing the development cycles of chips for wireless communications, broadband networking, PCs, tablets and other segments. We provide technology for rapid electromagnetics modeling, RF component synthesis, and signal integrity of silicon ICs and Systems-in-Package. Our solutions have been adopted by several major semiconductor companies since 2000. Helic is headquartered at 101 Montgomery Street, suite 2650, San Francisco, CA 94104.

For additional information please contact: Nikolas Provatas, T: +1.866.994.3542

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