TSMC Helps LSI Reduce Leakage 25 Percent on Next Generation Product

PowerTrim gate length biasing optimizes power with no area or performance compromise

HSINCHU, Taiwan, January 6 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) (TWSE: 2330,
NYSE: TSM) today announced that LSI Corporation achieved over 25% overall
leakage reduction in a next generation product by implementing TSMC's
PowerTrim power optimization technology on the company's 65nm low power (LP)
process.

PowerTrim is a first-of-its-kind technology that blends a layer of design
technology with advanced semiconductor processing to optimize a design's
power leakage. Tela Innovations provides the patented PowerTrim technology
and services under an exclusive license to TSMC.

PowerTrim software analyzed the LSI design and substituted cells with
small increases in gate length on non-critical timing paths. These small
changes make a significant impact since increasing gate length exponentially
reduces leakage current.

"Low power consumption and high performance are key to the success of our
products," said Norm Lawrence, director of Product and Test Engineering,
Networking Components Division at LSI Corporation. "Working closely with TSMC
and Tela Innovations, PowerTrim helped us reduce leakage power by over 25%
while improving our yield distribution for leakage."

PowerTrim performs speed/power tradeoffs using a CD biasing technique
that analyzes designs and intelligently applies gate length biases to the
appropriate cells (i.e. non-critical paths possessing sufficient timing
"slack"). The technology optimizes transistors along these paths without
reducing chip performance. The gate CD biases are implemented as part of the
Optical Proximity Correction (OPC) flow. The process does not impact cell
footprint or chip area. The result is significant leakage power reduction
while maintaining chip performance and area. PowerTrim also significantly
reduces leakage power variability resulting in improved parametric yield.

"Enabling our customers to improve important product features like power
consumption is one of the key objectives of TSMC's Open Innovation
Platform(TM) initiative," said ST Juang, senior director of Design
Infrastructure Marketing at TSMC. "Collaborating with innovative companies
like Tela Innovations to provide an Open Innovation(TM) program creates
differentiated value that is the central vision behind this initiative. We
are quite pleased with the results that LSI achieved and are encouraged by
their decision to deploy PowerTrim."

The PowerTrim service is implemented in conjunction with other leakage
reduction techniques such as multi-Vt cell libraries, reverse body biasing,
header/footer sleep switches, and voltage islands. It provides additional
leakage improvements and is more efficient in terms of leakage reduction per
unit of slack than high-Vt transistors.

Availability

PowerTrim is available directly from TSMC for advanced process
technologies including 90nm, 80nm, 65nm, 55nm, and 40nm process nodes. Tela's
technology is exclusively embedded in PowerTrim. Contact TSMC account
management for more information.

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing
the industry's leading process technology and the foundry's largest portfolio
of process-proven libraries, IP, design tools and reference flows. The
Company's total managed capacity in 2009 exceeded 10 million 8-inch
equivalent wafers, including capacity from two advanced 12-inch -
GigaFabs(TM), four eight-inch fabs, one six-inch fab, as well as TSMC's
wholly owned subsidiaries, WaferTech and TSMC (China), and its joint venture
fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities.
Its corporate headquarters are in Hsinchu, Taiwan. For more information about
TSMC please visit www.tsmc.com.

Ferda Mehmet of A&R Edelman, +1-650-762-2946, mobile, +1-415-308-7877 for TSMC; or Michael Kramer, Corporate Public Relations of TSMC, +886-3-5636688 ext: 7126216